NAND memory integrated circuit chips are well known in the art. In a NAND memory chip, the memory is characterized by a number of blocks of storage, with each block containing a number of pages. The total amount of storage in each block is the minimum erasable unit. Further, each page contains a number of memory cells. In the past, a memory cell has stored a single bit, so called SLC (Single Level Cell). However, more recently, manufacturers of NAND memory integrated circuit chips have stored multi bits in each memory cell, so called MLC (Multi Level Cell). Whether memory cells are SLC or MLC, the charges stored in each cell may degrade. To recover “corrupt” or degraded data, data bits are accompanied by ECC (Error Checking and Correction) bits. These ECC bits are also stored in the accompanying memory cells of the NAND chip and are used to check for errors in the data cells and to correct them using well known algorithms, such as Reed-Solomon and BCH algorithms.
The problem with ECC bits is that as a NAND memory chip ages, the number of error bits will increase. This increase, however, affects performance non-linearly. Thus, if a 1 KB of data bits is read, and the NAND memory chip is “fresh” and relatively error free, the time required to check and correct output data bits may be only on the order of 0.5 usec. However, as the NAND memory chip ages, and more error bits occur, the same 1 KB of data bits may require 10 usec to be checked, corrected and outputted from the NAND memory chip. From the stand point of a system designer, the unpredictability of the performance is an area of concern. Thus, it is desired that even as a NAND memory chip ages and the number of error bits increases, the performance or the total amount of time required to read the same amount of data (including any checking and correction required) does not degrade.
Referring to FIG. 1 there is shown an output buffer circuit 10 of the prior art. A NAND memory 12 provides data output. The data bits and the accompanying ECC bits are supplied to a first multiplexer 14. From there the data is supplied either to a first buffer 16 or a second buffer 18. From the first buffer 16 or the second buffer 18, the data is supplied to a second MUX 20 as the output of the buffer circuit 10. The buffer circuit 10 is known as ping-pong circuit. In operation, the circuit 10 functions as follows. In a rust clock cycle T1, the data from the NAND memory 12 is passed through MUX 14 and is stored in buffer 16. The data in the buffer 16 is checked and corrected by ECC checking and correction circuits (not shown) if need be. In a second clock cycle T2, the data from the NAND memory 12 is passed through MUX 14 and stored in buffer 18 and the data in the buffer 18 is checked and corrected by ECC checking and correction circuits (not shown) if need be, while the data from the buffer 16 is passed through the MUX 20 as the output of the buffer circuit 10. In a third clock cycle T3, the data from the NAND memory 12 is passed through MUX 14 and stored in buffer 16 and the data in the buffer 16 is checked and corrected by ECC checking and correction circuits (not shown) if need be, while the data from the buffer 18 is passed through the MUX 20 as the output of the buffer circuit 10
From the foregoing, it can be seen that the buffer circuit 10 of the prior art maintains the consistency of performance even as ECC degrades over time, so long as the error checking and correction can be performed in one clock cycle. However, this assumption is not true as more NAND memory chips use MLC memory cells and as the number of associated error correction bits increase. Hence there is a need to maintain the consistency of performance for a NAND memory chip even as ECC degrades over time.